This invention relates to elastic storage apparatus and more particularly to such apparatus for storing digital information according to predetermined synchronization patterns.
A telephone system is a prime example of a communications network where information is transmitted between various points or nodes according to a switching path set up by the communications network in order to enable one subscriber to communicate with another. In such systems, synchronous time-division multiplexed data is transferred at a constant rate between the various nodes so that the amount of information entering one terminal or node is in balance with the information exiting that same node. Each terminal of the transmission link is provided with a local clock source adapted to control operations at that particular terminal. In regard to the system in general, it is desirable that a common stable clock frequency be provided to all nodes which form part of the synchronous network. At the transmitting terminal, the local clock operates to generate bits and framing pulses which serve to align outgoing data in appropriate time slots. The data is further assembled within frames where each frame has a fixed number of bits and framing bits are further inserted in order to enable the receiving terminal to disassemble the data and recover the transmitted information in each of the time slots.
In a practical system, while the average frequency of each of the terminal clocks can be maintained relatively constant, the instantaneous phase relationship between the information streams transmitted and received are not known and are subjected to random variations generally referred to as phase jitter. Phase jitter can be considered equivalent to short term frequency errors which tend to average out over long periods of time, but which can adversely affect short term data.
Basically, any increase in input frequency relative to output frequency essentially means that more data is entering a node than is leaving a node. Both conditions require that some information be stored temporarily at each node in a so-called elastic store to allow for the phase jitter and unknown phase relationships. For example, typical transmission links such as cables and so on are associated with propagation delay and behave as a delay line for the data train. In any event, even though the clocks are synchronized in frequency, the data can be out of frame synchronization because of the propagation delay on the links carrying the data between a transmit and a receiving terminal. In such systems, the incoming data train can have any phase and frame relationship with respect to the local clock. To compensate for this problem, as well as phase jitter on the data stream, one must delay the data train at the receiving terminal according to the random variation which can occur. Circuit configurations for providing such a delay are sometimes referred to in the prior art as elastic stores, which circuits can handle both the delay for frame synchronizing the data stream and the delay for compensating other phase changes which may be due to temperature and so on. The amount of delay or storage required by such a system is typically a function of magnitude of the phase jitter, propagation delay and the acceptable slip rate, as described below.
Data information streams are constructed with formats which allow the receiving node to identify the start of a message word and to further distinguish each bit of the word. Accordingly, bit, word and frame identification can all be extracted from the information stream. When phase shifts due to jittering are not cancelled or compensated for, the accumulated data shift may cause the elastic store to empty or overflow and hence, a "slip" is said to have occurred. The basic function of an elastic store apparatus is to minimize the loss of information caused by such slips. Basically, the receiving terminal must initiate an operation to relocate the incoming framing signal when it appears at the output of the store and to realign this newly located framing signal with the local clock framing signal.
According to prior art techniques, the delayed framing signal is first located, the local clock framing pulse is then located and one can determine the phase lead or lag of the delayed framing signal with respect to the clock pulse. Once the actual delay is calculated, the store is then increased or decreased an appropriate amount to correct the delay of the incoming frame signal to re-establish frame synchronization. Circuitry for doing this is relatively complicated.
Other techniques such as that shown in U.S. Pat. No. 3,887,769 entitled FRAME SYNCHRONIZATION OF ELASTIC DATA BIT STORES issued on June 3, 1975 to M. P. Cichetti, Jr. et al depicts techniques employing shift register stages which delay incoming frames of data to align each frame with framing pulses of a local clock. The circuitry operates to compensate for jitter of the incoming data stream by providing a variable delay obtained through a counter whose count defines the register output stage. In this type of system, framing synchronization is initially obtained or regained when lost by first determining when the framing signal shifts to the output stage and then the count is advanced at the incoming bit rate to define each successive stage when the framing signal shifts to the stage and to halt any advance when a local framing pulse is generated. If the count in this system advances to define a final one of the register stages, the count is then reduced by a number equal to the number of bits in a frame. If the count is decreased to define an initial stage, the count is increased by the same number.
The system depicted in the above noted reference is extremely complicated and requires a large number of components to implement elastic storage and the attendant compensation.
It is therefore an object of the present invention to provide improved apparatus for elastic storage and synchronization control of serial digital data.